1. Field of the Invention
The present invention relates generally to a semiconductor memory device and, more particularly, to a differential correlated double sampling sense amplifier for use in a DRAM semiconductor device.
2. Description of the Related Art
An increasing number of electronic equipment and electronic-based systems require some form of high-speed memory devices for storing and retrieving information (or "data"). While the types of such memory devices vary widely, semiconductor memory devices are most commonly used in memory applications requiring implementation in a relatively small area. Within this class of semiconductor memory devices, the DRAM (Dynamic Random Access Memory) is one of the more commonly used types.
The DRAM has memory arrays consisting of a number of intersecting row and column lines of individual transistors or memory cells. In a conventional dynamic random access memory (DRAM) device each memory cell, or memory bit, consists of one transistor and one capacitor. A terminal of the transistor is connected to a digit line, or bitline, of the memory device. Another terminal of the transistor is connected to a terminal of the capacitor and the gate terminal of the transistor is connected to a wordline of the memory device. The transistor thus acts as a gate between the digit line and the capacitor.
The second terminal of the capacitor is connected to a voltage rail which carries a voltage, such as Vcc/2. Thus, when the wordline for a particular cell is active, the gate transistor is in a conducting state and the capacitor is connected to the digit line. The capacitor stores a charge that, depending on whether the capacitor is charged or discharged, represents either a logic high or a logic low value.
Typically, a microcomputer circuit selects (or activates) particular row and column lines to access selected memory cells. "Access" typically refers to reading data from or writing data to selected memory cells. Reading data from the memory cells involves the use of a sense amplifier to detect whether the voltage level stored in the memory cell represents a binary one (logic high) or a binary zero (logic low).
Memory devices are typically constructed with complementary digit lines of equal capacitance. Sense amplifiers are connected between the digit lines and operate to sense the differential voltage across the digit lines. Before a memory cell is selected for access, the complementary digit lines must be equilibrated to minimize the cell access time. Equilibration circuits typically short the complementary digit lines together, resulting in an equilibrate voltage equal to the voltage midpoint between the two equal capacitance and logically opposite digit lines. Conventionally, a DRAM contains one sense amplifier for a designated group (row or column) of memory cells. If the voltage level stored in the memory cell represents a binary zero, one of the digit lines will increase in level., typically to a supply voltage Vcc, and the other digit line will decrease in level, typically to a ground level. If the voltage level stored in the selected memory cell corresponds to a binary one, a change in the opposite direction occurs. Through this complementary operation, the sense amplifier yields a single output signal which is coupled through an output buffer to an output pin of the DRAM device.
FIG. 1 illustrates a sense amplifier 10 and related circuitry of a DRAM device having a first array ARRAY020 and a second array ARRAY122, each of which comprises a plurality of memory cells 21 (shown in ARRAY020). A sense amplifier 10 senses charge stored in the selected memory cell of the selected array 20, 22 via a voltage differential on the pair of digit lines D024 and D0* 26. One of the arrays 20, 22 is selected by application of signals ISOa and ISOb to transistors 32a, 32b and 34a, 34b, respectively. Thus, when ISOa is driven to a logic high value and ISOb is driven to a logic low value, transistors 32a and 32b become conductive, i.e., turn on, to connect ARRAY020 to sense amplifier 10 while transistors 34a and 34b do not conduct, i.e., turn off, to isolate ARRAY122 from sense amplifier 10. When ISOa is driven to a logic low value and ISOb is driven to a logic high value, transistors 34a and 34b turn on to connect ARRAY122 to sense amplifier 10 while transistors 32a and 32b turn off to isolate ARRAY020 from sense amplifier 10.
To minimize the cell access time, equilibration circuits 50a and 50b are provided. Equilibration circuit 50a includes transistor 54 with a first source/drain region coupled to digit line D024, a second source/drain region coupled to digit line D0* 26 and a gate coupled to receive an equilibration signal EQa. Equilibration circuit 50a further includes first and second transistors 56 and 58. Transistor 56 includes a first source/drain region that is coupled to digit line D024, a gate that is coupled to receive the equilibration signal EQa and a second source/drain region that is coupled to receive an equilibration, voltage Veq, which is typically equal to Vcc/2. Second transistor 58 includes a first source/drain region that is coupled to digit line D0* 26, a gate that is coupled to receive the equilibration signal EQa and a second source/drain region that is coupled to the equilibration voltage Veq. When the signal EQa is at a high logic level, equilibration circuit 50a effectively shorts digit line D024 to digit line D0* 26 such that both lines are equilibrated to the voltage Veq. Equilibration circuit 50b is constructed in a similar manner to equilibration circuit 50a and operates when the EQb signal is at a high logic level.
When sense amplifier 10 has sensed the differential voltage across the digit lines D024 and DO*26, a signal representing the charge stored in the accessed memory cell is output from the DRAM device on the input/output (I/O) lines I/O 36 and I/O* 38 by connecting the I/O lines I/O 36 and I/O* 38 to the digit lines D024 and D0* 26, respectively. A column select (CSEL) signal is applied to transistors 40, 42 to turn them on and connect the digit lines D024 and D0* 26 to the I/O lines I/O 36 and I/O* 38.
FIG. 2 illustrates the sense amplifier block 10 of FIG. 1. A typical sense amplifier includes a P-sense amplifier 70 and an N-sense amplifier 80. These amplifiers work together to detect the access signal voltage and drive the digit lines D024 and D0* 26 to Vcc and ground accordingly. As shown in FIG. 2, the N-sense amplifier 80 consists of cross-coupled NMOS transistors 82, 84 and drives the low potential digit line to ground. Similarly, the P-sense amplifier 70 consists of cross-coupled PMOS transistors 72, 74 and drives the high potential digit line to Vcc. The NMOS pair 82, 84 or N-sense-amp common node is labeled NLAT* (for N-sense-amp LATch). Similarly, the P-scnse-amp 70 common node is labeled ACT (for ACTive pull-up). Initially, NLAT* is biased to Vcc/2 and ACT is biased to ground. Since the digit line pair D024 and D0* 26 are both initially at Vcc/2 volts, the Nsense-amp transistors 82, 84 remain off due to zero Vgs potential. Similarly, both P-sense-amp transistors 72, 74 remain off due to their negative Vgs potential. As discussed in the preceding paragraph, a signal voltage develops between the digit line pair 24, 26 when the memoir cell access occurs. While one digit line contains charge from the cell access, the other digit line serves as a reference for the sensing operation. The sense amplifier firing generally occurs sequentially rather than concurrently. The N-sense-amp 80 fires first and the P-sense-amp 70 second. Dropping the NLAT* signal toward ground will fire the N-sense-amp 80. As the voltage between NLAT* and the digit lines approaches Vth, the NMOS transistor whose gate connection is to the higher voltage digit line will begin to conduct. Conduction results in the discharge of the low voltage digit line toward the NLAT* voltage. Ultimately, NLAT* will reach ground, bringing the digit line with it. Note that the other NMOS transistor will not conduct since its gate voltage derives from the low voltage digit line, which is discharging toward ground.
Shortly after the N-sense-amp 80 fires, ACT will be driven toward Vcc. This activates the P-sense-amp 70 that operates in a complementary fashion to the N-sense-amp 80. With the low voltage digit line approaching ground, a strong signal exists to drive the appropriate PMOS transistor into conduction. This will charge the high voltage digit line toward ACT, ultimately reaching Vcc. Since the memory bit transistor remains on during sensing, the memory bit capacitor will charge to the NLAT* or ACT voltage level. The voltage, and hence charge, which the memory bit capacitor held prior to accessing will restore a fill level, i.e., Vcc for a logic one and GND for a logic zero.
There are potential problems, however, with the sense amplifier circuit 10 as illustrated in FIG. 2. For example, when the sense amplifier circuit 10 is first connected to ground and the bias power supply, an offset can exist at the output nodes due to mismatches in transistor threshold voltages, device sizes, drain conductance and transconductance of transistors 72, 74 and 82, 84. This offset can be reflected back into the input as an input offset, and will add to any mismatch of offset in the pre-charge voltages. In application as a DRAM sense amplifier, the signal on the digit lines must be much larger than this offset to provide accurate sensing of the signal representing the charge stored in the memory bit capacitor.
As device dimensions become smaller and smaller it becomes more and more difficult to achieve matching characteristics of transistors 72, 74, 82 and 84 due to larger variations in threshold voltages caused by number fluctuations in impurity dopings, larger variations in drain conductance and percentage variations in device dimensions. In addition, the use of lower power supply voltages means lower digit line signals. Consequently, it becomes more and more difficult to accurately detect digit line data using conventional techlliclues.